1. Field of the Invention
The present invention relates to an analog to digital converter, and more particularly, to an analog to digital converter which is suitable for processing serial data at a fast rate.
2. Description of the Related Art
In general, an analog to digital converter (ADC) converts an analog signal into a digital signal over a preset time. The structure of an ADC, or a digital to analog converter (DAC), is dependent on a circuit technology used to fabricate the chip on which the ADC or DAC is located. The ADC is usually used as one function of a multi-function chip which requires serial data, rather than a parallel output. Such an ADC is required to have a high performance (e.g., a fast output data rate), and accurate data processing of the ADC is also required. However, a related art serial-processing-type ADC cannot satisfy the two requirements of fast rate data processing and high performance. Accordingly, a parallel ADC is used instead, which has the undesired requirement of an increased number of pins. Therefore, an interest in development of an ADC that permits processing of a serial data at a fast rate is ever increasing.
The related art ADC will be explained with reference to the attached drawing FIGS. 1-3. FIG. 1 illustrates a block diagram of a related art serial ADC, in which an analog signal Vin is converted into a digital signal synchronous to a reference strobe signal REF_STB and a reference clock signal REF_CLK. The digital signal is forwarded as a digital output DATA_OUT(n) in series at preset timings. One example of such a related art serial ADC may be found in xe2x80x9cReference refreshing cyclic analog to digital and digital to analog convertersxe2x80x9d (IEEE Journal Of Solid-State Circuits, Vol. SC-21. No. 4. Aug. 1986).
FIGS. 2 and 3 illustrate a related art algorithmic ADC and its signals, in which a strobe signal Vstb is in a high state (not shown) during a period T3 of a reference clock signal CLK_REF when CLK_REF is in a low state, and a first switch S1 is connected to an analog input terminal Vin. The voltage provided to a sample/hold unit 11 is sampled and held. The held voltage is multiplied by two in the multiplier 12, to produce voltage Va. The voltage Va from the multiplier 12 is compared to a reference voltage VREF in a high period T3 of the reference clock signal CLK_REF, to determine a data VOUT. VOUT is provided in series during a low period T4 of the reference clock signal CLK_REF. In this instance, the provided signal VOUT becomes the most significant bit (MSB) of the output data DATA_OUT(8), which is D7 if the output data has 8 bits.
In the meantime, the strobe signal Vstb is in a high state only in a low portion of the T3 period of the reference clock signal CLK_REF, and is held in a low state (not shown) until period T11 of the reference clock signal CLK_REF. That is, the strobe signal Vstb is in the low state until the strobe signal Vstb transitions to high (not shown) in a low period T12 of CLK_REF, because a reference strobe signal REF_STB transitions to high in T10. Then, when the MSB is fixed in period T4 of the reference clock signal CLK_REF, a voltage provided from a second switch S2 is determined by the MSB, VOUT. Then, the voltage from the second switch S2 becomes Va-Vs2, and is forwarded during a low period T5 of CLK_REF through the sample/hold unit 11, the multiplier 12, and the comparator 13, thereby fixing the next bit value D6 of the DATA_OUT. This process is continued over successive clock cycles until all bits (Dnxe2x88x921 to D0) are generated.
Referring to FIG. 3, digital outputs DATA_OUT(8) are provided in series at preset timings synchronous to the reference strobe signal REF_STB and the clock signal CLK_REF by repeating the aforementioned process. Clocks each having a rising edge are generated as many times as the number of desired bits of the serial data during outputting the serial data DATA_OUT(8), to provide an external clock signal CLK_OUT. However, if the analog signal Vin provided in response to the strobe signal Vstb contains an error caused as the analog signal Vin passes through the sample/hold unit and the multiplier (i.e., the analog signal Vin has a difference from the Va), this error or difference is Voffset in the MSB. Then, the next bit""s voltage is multiplied by two in the multiplier, and the resulting error in the next-most significant bit is {(Voffsetxc3x972)+Voffset}. Thus, the inherent error Voffset in the related art ADC increases by 2n as a number of bits xe2x80x9cnxe2x80x9d increases, and the related art algorithmic ADC cannot provide accurate digital data.
Accordingly, the present invention is directed to an analog to digital converter that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an analog to digital converter circuit includes a clock control block for providing first and second internal clock signals; a parallel analog to digital converter for receiving and converting an analog signal into parallel digital data synchronously with the first internal clock signal; and a parallel to serial transform logic control block for transforming the parallel digital data into serial digital data synchronously with the second internal clock signal.
In accordance with another aspect of the invention, a method for converting an analog input signal into a serially output digital signal includes converting the analog input signal into parallel digital data synchronously with a first clock signal; and transforming the parallel digital data into the serially output digital signal synchronously with a second clock signal.
An advantage of the present invention is providing an analog to digital converter which increases the accuracy of the output data, and which is suitable for providing serial data at a fast rate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.